Arh, that is actually a good question. Also i wonder if Intel are then making more profits from every tick? Since every node you save roughly 45% of die size. i.e Roughly Double the transistor in same die space.
Tick dies are always smaller than Tock dies. Initial production volumes for the new process are lower than the mature one (both in number of wafers, and defect rates); so the CPU only sees incremental gains in transistor count. Then as the process matures and a new more complex architecture launches in the Tock the die size jumps back up to roughly the same size as the old Tock.
Why should we expect only 20% more transistors when the lithography size is reduced to 69% of the former size?
Since the transistors generally scale in both dimensions (i.e., length and width both smaller), I would expect the transistor count to go up by even more than that implied by a 31% reduction in scale. Probably less than double the former transistor count, but not by a lot. Certainly 50% increase does not seem high.
Of course, things are more complicated with Ivy Bridge, since it will use the new multiple-gate transistors. But I would not expect that to make a big difference.
Besides, Moore's law for transistor counts says it should double every 18 months. So it seems your "typical 20%" does not make sense from either a geometry standpoint or from the standpoint of Moore's law.
Correction: Moore's law for transistor counts specifies a doubling every two years. But since there is a "tick" every two years, that means a tick should be a double in transistor count if Moore's law still holds.
I believe you may be confusing a few things. Going from 28nm to 22nm doesn't require, in principle, any change in the number of transistors. So, in theory, Intel could do a die-shrink of SB and port it 1:1 to 22nm with the same exact transistor count (1.16B). The fact that the node is smaller, doesn't mean that all transistors are smaller. Power-gating transistors, for example, are usually very large and don't scale with technology. However, in a CPU, the majority of the area is occupied by minimum-size logic gates, which shrink directly from 28nm to 22nm.
It seems though that you're trying to keep the die area constant, which it does not: one of the reasons to go to a smaller node is to be able to have smaller chips, so that the cost-per-transistor is lower. Think about making 1.16B transistors in the 0.18um node, which was used for the Pentium III: the die size would be huge.
The "typical 20%" comes from the fact that every technology shrink, Intel makes some upgrades to the architecture: maybe a bit more cache, and, in this case, a new GPU core. It is not really related to the % of shrink. The Moore's law is also something different, as it refers to the doubling of transistors per unit area, which is approximately kept going down to 22nm.
28nm? What is that? Sandy Bridge is 32nm. Ivy Bridge is 22nm.
Anyway, not confused, I was asking what basis does he expect a 20% increase. I'm aware the die size usually decreases on a tick.
I suppose the answer to my question is that he expects 20% on the basis of past ticks being about 20%. But if that is his basis, then it would have been a much better article if he listed the transistor count changes for all previous ticks.
Please try to read and UNDERSTAND the article before posting nonsense comments.
The article was about the difference between what Anand EXPECTED (about 20% increase) and what the actual increase was. Anand was initially surprised about the increase (when he had the wrong counts), but with the corrected counts, he says it is about what he would expect.
First off, Moore's law doesn't have anything to do with transistor counts. It has to do with transistor density. Why will transistor count magically increase if you're shrinking the same design to a smaller node?
In fact, the only increase will come from the new features being added. You cannot predict it with math as you're trying to do in your first comment. So you shouldn't really be "expecting" anything particular from the tick unless you know what features are being added. You can either save costs by building the same features on a smaller die or add more features on the same size die, or any combination of the two.
Conroe (65nm Core 2 Duo) had 291 million transistors on a 143mm² die, while Wolfdale (45nm Core 2 Duo) had 410 million transistors on a 107mm² die. In this case the transistor count increase was 40% (mostly for the bigger L2) and die size was decreased as well, which means Intel opted to go for a combination of saving costs and adding more transistors.
If you calculate average transistor densities, they're 2.03 million per mm² for Conroe and 3.8 million per mm² for Wolfdale, a near doubling according to Moore's law.
BTW, the quote you supplied in fact has to deal with DENSITY, not actual count.
Moore's Law is about how much you can pack within a given area. It doesn't NOT necessarily require an increase in transistor count for a given IC design.
You're looking at different sides of the same coin. Neither one of of you are wrong.
"The number of transistors that _CAN_ be placed _inexpensively_ on an integrated circuit doubles approximately every two years."
Notice the word "can". It doesn't mean manufacturers have to keep doubling the transistor counts. It just means that they can do so for the same cost. In other words, transistors become half as costly with every step. That is, the transistor density keeps doubling and so the amount of silicon needed keeps getting halved.
Dude, are you st00pid or something ? Just because manufacturer's production process moves to a new node this doesn't imply that they ABSOLUTELY MUST double the number of transistors in their circuit just for the sake of moving from one node to another.
Sorry for the late response on this, but it's actually quite simple. The rule of thumb is to either introduce a new architecture or a new process, never both. The risk in jumping to a new process node is very high. Yields start out very low, there are bound to be issues that you didn't plan on and you have very little existing experience (other than test chips) on the process. Note that these problems only increase with larger chips, they don't get any easier.
The risk in moving to a new architecture is just as big. There are a ton of unknowns. Even just increasing the size of a chip on a brand new process is super risky as I mentioned above.
This is where tick-tock comes from. You introduce a new process on a relatively unchanged design, or you introduce a new design on an existing process. The reason we don't get a huge increase in transistor count on IVB is because Intel is trying to play it safe as this is its first 22nm chip.
There are also economic factors. The first 22nm wafers will be more expensive to produce than their 32nm counterparts, so you often have to build a smaller chip in order to maintain profit margins - at least initially.
I look forward to getting the juice and details of the upcoming uARCHs and all the crazy new stuff intel is cooking up for their chips...Where is all the SB-E info? where is an IVY-B onstage crazy demo?
where all the uARCH details of the new chips? This IDF we get a solar powered demo and a bunch of Thunderbolt products...so boring ZZZZZZZ
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JMS3072 - Thursday, September 15, 2011 - link
Wouldn't Ivy Bridge's transistor count likewise balloon when it gets laid out at the fab?Sagath - Thursday, September 15, 2011 - link
Yes, unless the 1.4B count is already the fab count, and not the schematic count.iwodo - Thursday, September 15, 2011 - link
Arh, that is actually a good question. Also i wonder if Intel are then making more profits from every tick? Since every node you save roughly 45% of die size. i.e Roughly Double the transistor in same die space.JMS3072 - Thursday, September 15, 2011 - link
I'd imagine so, but they also have to pay R&D to get the node shrunk...which I can't imagine would be cheap.DanNeely - Thursday, September 15, 2011 - link
Tick dies are always smaller than Tock dies. Initial production volumes for the new process are lower than the mature one (both in number of wafers, and defect rates); so the CPU only sees incremental gains in transistor count. Then as the process matures and a new more complex architecture launches in the Tock the die size jumps back up to roughly the same size as the old Tock.bahamakyle - Friday, September 16, 2011 - link
'Both are correct, but the 1.16B number is directly comparable to Ivy Bridge's 1.4B transistors.'The 1.4B number is already the ballooned fab value.
jwilliams4200 - Thursday, September 15, 2011 - link
Why should we expect only 20% more transistors when the lithography size is reduced to 69% of the former size?Since the transistors generally scale in both dimensions (i.e., length and width both smaller), I would expect the transistor count to go up by even more than that implied by a 31% reduction in scale. Probably less than double the former transistor count, but not by a lot. Certainly 50% increase does not seem high.
Of course, things are more complicated with Ivy Bridge, since it will use the new multiple-gate transistors. But I would not expect that to make a big difference.
Besides, Moore's law for transistor counts says it should double every 18 months. So it seems your "typical 20%" does not make sense from either a geometry standpoint or from the standpoint of Moore's law.
jwilliams4200 - Thursday, September 15, 2011 - link
Correction: Moore's law for transistor counts specifies a doubling every two years. But since there is a "tick" every two years, that means a tick should be a double in transistor count if Moore's law still holds.yankeeDDL - Thursday, September 15, 2011 - link
I believe you may be confusing a few things.Going from 28nm to 22nm doesn't require, in principle, any change in the number of transistors.
So, in theory, Intel could do a die-shrink of SB and port it 1:1 to 22nm with the same exact transistor count (1.16B).
The fact that the node is smaller, doesn't mean that all transistors are smaller. Power-gating transistors, for example, are usually very large and don't scale with technology.
However, in a CPU, the majority of the area is occupied by minimum-size logic gates, which shrink directly from 28nm to 22nm.
It seems though that you're trying to keep the die area constant, which it does not: one of the reasons to go to a smaller node is to be able to have smaller chips, so that the cost-per-transistor is lower. Think about making 1.16B transistors in the 0.18um node, which was used for the Pentium III: the die size would be huge.
The "typical 20%" comes from the fact that every technology shrink, Intel makes some upgrades to the architecture: maybe a bit more cache, and, in this case, a new GPU core. It is not really related to the % of shrink.
The Moore's law is also something different, as it refers to the doubling of transistors per unit area, which is approximately kept going down to 22nm.
jwilliams4200 - Thursday, September 15, 2011 - link
28nm? What is that? Sandy Bridge is 32nm. Ivy Bridge is 22nm.Anyway, not confused, I was asking what basis does he expect a 20% increase. I'm aware the die size usually decreases on a tick.
I suppose the answer to my question is that he expects 20% on the basis of past ticks being about 20%. But if that is his basis, then it would have been a much better article if he listed the transistor count changes for all previous ticks.
ssj4Gogeta - Thursday, September 15, 2011 - link
He's not "expecting" or predicting anything. He's just stating what Intel _told_ him.jwilliams4200 - Thursday, September 15, 2011 - link
Did you not read the article?"That puts Ivy Bridge's transistor count at 20.7% higher than Sandy Bridge, which is more in line with what to EXPECT from a tick."
It does NOT say that Intel told him to expect a 20% increase.
ssj4Gogeta - Thursday, September 15, 2011 - link
"It turns out that was wrong as Intel's Mooly Eden accidentally read the B in billion as an 8 while on stage. The real number is 1.4 billion."1.4/1.16 = 1.206
jwilliams4200 - Thursday, September 15, 2011 - link
Please try to read and UNDERSTAND the article before posting nonsense comments.The article was about the difference between what Anand EXPECTED (about 20% increase) and what the actual increase was. Anand was initially surprised about the increase (when he had the wrong counts), but with the corrected counts, he says it is about what he would expect.
ssj4Gogeta - Thursday, September 15, 2011 - link
First off, Moore's law doesn't have anything to do with transistor counts. It has to do with transistor density. Why will transistor count magically increase if you're shrinking the same design to a smaller node?In fact, the only increase will come from the new features being added. You cannot predict it with math as you're trying to do in your first comment. So you shouldn't really be "expecting" anything particular from the tick unless you know what features are being added. You can either save costs by building the same features on a smaller die or add more features on the same size die, or any combination of the two.
Conroe (65nm Core 2 Duo) had 291 million transistors on a 143mm² die, while Wolfdale (45nm Core 2 Duo) had 410 million transistors on a 107mm² die. In this case the transistor count increase was 40% (mostly for the bigger L2) and die size was decreased as well, which means Intel opted to go for a combination of saving costs and adding more transistors.
If you calculate average transistor densities, they're 2.03 million per mm² for Conroe and 3.8 million per mm² for Wolfdale, a near doubling according to Moore's law.
jwilliams4200 - Thursday, September 15, 2011 - link
No, you are completely wrong. Moore's Law does refer to transistor counts on ICs. A common statement of the law is:"The number of transistors that can be placed inexpensively on an integrated circuit doubles approximately every two years."
Which still does not answer the question, on what basis does Anand "expect" transistor counts to increase by about 20% for a tick?
Stahn Aileron - Thursday, September 15, 2011 - link
BTW, the quote you supplied in fact has to deal with DENSITY, not actual count.Moore's Law is about how much you can pack within a given area. It doesn't NOT necessarily require an increase in transistor count for a given IC design.
You're looking at different sides of the same coin. Neither one of of you are wrong.
Stahn Aileron - Thursday, September 15, 2011 - link
*It does NOT necessarily...jwilliams4200 - Thursday, September 15, 2011 - link
Density is number of transistors per square millimeter (or some other unit). That is NOT what the statement of Moore's law that I quoted says.ssj4Gogeta - Thursday, September 15, 2011 - link
In fact, that is what it means."The number of transistors that _CAN_ be placed _inexpensively_ on an integrated circuit doubles approximately every two years."
Notice the word "can". It doesn't mean manufacturers have to keep doubling the transistor counts. It just means that they can do so for the same cost. In other words, transistors become half as costly with every step. That is, the transistor density keeps doubling and so the amount of silicon needed keeps getting halved.
Arnulf - Friday, September 16, 2011 - link
Dude, are you st00pid or something ? Just because manufacturer's production process moves to a new node this doesn't imply that they ABSOLUTELY MUST double the number of transistors in their circuit just for the sake of moving from one node to another.Anand Lal Shimpi - Sunday, September 18, 2011 - link
Sorry for the late response on this, but it's actually quite simple. The rule of thumb is to either introduce a new architecture or a new process, never both. The risk in jumping to a new process node is very high. Yields start out very low, there are bound to be issues that you didn't plan on and you have very little existing experience (other than test chips) on the process. Note that these problems only increase with larger chips, they don't get any easier.The risk in moving to a new architecture is just as big. There are a ton of unknowns. Even just increasing the size of a chip on a brand new process is super risky as I mentioned above.
This is where tick-tock comes from. You introduce a new process on a relatively unchanged design, or you introduce a new design on an existing process. The reason we don't get a huge increase in transistor count on IVB is because Intel is trying to play it safe as this is its first 22nm chip.
There are also economic factors. The first 22nm wafers will be more expensive to produce than their 32nm counterparts, so you often have to build a smaller chip in order to maintain profit margins - at least initially.
I hope this helps!
Take care,
Anand
mlkmade - Thursday, September 15, 2011 - link
I look forward to getting the juice and details of the upcoming uARCHs and all the crazy new stuff intel is cooking up for their chips...Where is all the SB-E info? where is an IVY-B onstage crazy demo?where all the uARCH details of the new chips? This IDF we get a solar powered demo and a bunch of Thunderbolt products...so boring ZZZZZZZ
ssj4Gogeta - Thursday, September 15, 2011 - link
For some reason I don't see articles listed on the homepage. You can find the IDF articles here:http://www.anandtech.com/pipeline/